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G8MNY  > TECH     12.06.15 12:23l 55 Lines 2475 Bytes #999 (0) @ WW
BID : 33018_GB7CIP
Read: GUEST
Subj: Locking a Frequency with 555
Path: IW8PGT<CX2SA<GB7CIP
Sent: 150612/0856Z @:GB7CIP.#32.GBR.EURO #:33018 [Caterham Surrey GBR]
From: G8MNY@GB7CIP.#32.GBR.EURO
To  : TECH@WW

By G8MNY                            (New Apr 15)
(8 Bit ASCII graphics use code page 437 or 850, Terminal Font)

Year ago I had a valve B&W 405 line camera that used many double triode
astables to lock the 50Hz frame to line interlaced 11250Hz line frequency!
I reworked it for 625 line by raising the 2x line LC osc to 31250Hz & looking
4x 1/5 he frequency astables to it (>6250>1250>250>50Hz) to correctly lock the
interlaced frame timebase.

The other day I had a simular problem, to lock a 1980s stereo coder design to
a modern RDS unit. This is normally done the other way around, locking RDS data
unit from the 19kHz pilot! The trouble with my approach was there was no clean
57kHz to start with! The Pic RDS generator had 6 data bits added to synthersize
the QPSK sine waves etc. So I used the MSB data to give the best 57kHz starting
clock.
                       +VeÄÄÄÄÄÂÄÄÄÄÄÄ4K7
                               ³     Preset
                               ³8      ³
                            ÚÄÄÁÄÄÄ¿7  1K
         Ú¿                 ³ +ve dÃÄÄÄ´ R
Very      ÀÙ     /\/\       ³      ³6 10K
Jitterty                    ³LM  thÃÄÄÄ´     ÚÄÄ¿  /\  /\
57KHz    ÄÄ33kÄÄÂÄÄÄÄ¿      ³555  tÃÄÄÄ´  ÀÄÄÙ    /  \/  \
Sqaure          ³  Lock    5³      ³2  ³ u1                 Jittery 19KHz
wave           ===  Pot<Ä´ÃÄ´CV   oÃÄÄÄ)Ä´ÃÄÄÄ10KÄÄÂÄÄ33KÄÄ>Ramp To Gently
             1n ³   4K7  u1 ÀÄÄÂÄÄÄÙ3  ³           ³        Lock Sine osc
                ³    ³        1³     C===3n3      ===2n7
         ÄÄÄÄÄÄÄÁÄÄÄÄÁÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄ

I found a slightly less jittery lock was obtained when both square waves were
ramped with a CR. The 555 19kHz astable is loosely locked to the 57kHz by
modulating the Control Voltage rail used to compaire the CR voltage. The
smaller the lock input the more loosley locked (higher Q) result, but less
stable to temp/Voltage changes. The C R components need to be high stability
types!

Result, after getting the ramps right & enough lock drive to the 555 19kHz
astable, it reliably locks up hot & cold, & with Wayne bridge sine osc gives a
stable locked osc in the right phase too in my application!

The above principle can be used for up & down locking of different frequencies
in many fractions etc. e.g. 50Hz from 60Hz.


See tech buls "Off Air Lock for Ref Osc.", & "Simple 1kHz AF Test Osc".



Why don't U send an interesting bul?

73 De John, G8MNY @ GB7CIP


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